Veryl: A Modern Hardware Description Language for Open-Source Computer Architecture
Published in Open Source Computer Architecture Research Workshop (2025)
Abstract:
Hardware Description Languages (HDLs) form the foundation of digital hardware design, yet many popular HDLs predate modern software engineering practices and lack the tooling ecosystem that has revolutionized software development. We present Veryl, a modern HDL designed as a SystemVerilog alternative that brings advanced safety features, improved developer ergonomics, and robust tooling to hardware development while maintaining seamless interoperability with existing SystemVerilog components. Veryl addresses key challenges in open-source hardware design through simplified syntax, clock domain safety analysis, generics for code reuse, real-time diagnostics, and comprehensive tooling. By lowering barriers to entry and enhancing developer productivity, Veryl contributes to a more accessible and collaborative open-source hardware design ecosystem.